The present disclosure relates generally to forming an semiconductor device and, more particularly, to forming dummy poly structures for a gate last process.
Semiconductor device geometries continue to dramatically decrease in size since such devices were first introduced several decades ago. Today's fabrication plants are routinely producing devices having feature dimensions less than 65 nm. However, solving the problems associated with implementing new processes and equipment technology while continuing to satisfy device requirements has become more challenging. For example, metal-oxide semiconductor (MOS) transistors have typically been formed with polysilicon gate electrodes. Polysilicon material has been used due to its thermal resistive properties during high temperature processing, which allows it to be annealed at high temperatures along with source/drain structures. Furthermore, polysilicon's ability to block the ion implantation of doping atoms into the channel region is advantageous, as it allows for the easy formation of self aligned source/drain structures after gate patterning is completed.
In some IC designs, there has been a desire to replace the polysilicon gate electrode with a metal gate electrode to improve device performance as feature sizes continue to decrease. A gate last process may be implemented to address the concerns of high temperature processing on metal materials. In a gate last process, a dummy poly gate is initially formed and processing may continue until deposition of an interlayer dielectric (ILD). The dummy poly gate may then be removed and replaced with a metal gate. However, problems arise when integrating a gate last process with other structures and devices typically found in semiconductor fabrication such as resistors, diodes, bipolar junction transistors (BJTs), monitor pads, alignment marks, and overlay marks.